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Process Simulation of Single Si Quantum Dot Formation for Single Electron Transistors
Prüfer, T.; Heinig, K. H.; Möller, W.; Hlawacek, G.; Xu, X.; Friedlund, C.; Djurabekova, F.; von Borany, J.
Conventional Lithography allows the fabrication of structures down to ~10 nm, being still too large for single electron transistors (SET) operating at room temperature (RT), which requires a tiny quantum dot (<5nm) embedded in SiO2, with tunnel distances to the source and drain <2nm. Here, we predict a fully CMOS-compatible method of self-assembly of a single Si quantum dot. We assume that 10…20nm thin nanopillars of a layer stack c-Si/6nm SiO2/30nm a-Si are made by conventional lithography. We predict that such a single dot is self-organized and self-assembled between the top and bottom silicon layer by phase separation of metastable SiOx. The SiOx is made by collisional mixing in the layer stack, which is simulated by TRI3DYN [1]. The phase separation of SiOx is described by 3D kinetic lattice Monte Carlo simulations [2]. Our results predict that a single Si nanodot forms if the volume of SiOx is smaller than (10nm)^3. This work has been funded by the European Union's Horizon 2020 research and innovation program under grant agreement No 688072.
[1] W. Möller; NIM B, 322, 23–33
[2] M. Strobel, K.H. Heinig, W. Möller, PRB 64, 245422
  • Lecture (Conference)
    DPG-Frühjahrstagung, 19.-24.03.2017, Dresden, Deutschland

Publ.-Id: 27014 - Permalink