Contact

Dr. Roland Beyer
PostDoc / Beamline scientist
Nuclear Physics
roland.beyerAthzdr.de
Phone: +49 351 260 - 3281

Mathias Kempe
student research assistant
Nuclear Physics

The nELBE (n,tot) Trigger Logic - FPGA 1

The trigger logic of the nELBE detector setup for neutron transmission measurements is realized by means of a FPGA logic based on the CAEN V1495 General Purpose Board. We developed a firmware for the "User FPGA" of this module that contains all logic functions needed for a proper operation of our setup.

The module processes 4 input signals and releases 29 output signals. The meaning of these signals is shown below. All parameters needed by the logical functions can be modified via VME write access to the corresponding register. The register Address Map is also shown below.

The logic schema is shown in the picture below. The input signals are the CFD signals of the 2 PMTs of the plastic scintillator, which have to be reduced in length and adjusted in time, so that they fulfil the coincidence conditions needed. The coincidence between both PMTs is done by the FPGA firmware. From the coincidence signal the raw trigger is created. The generation of the trigger is disabled if any veto signal is present.

The trigger is used to produce the TDC trigger and QDC gate and is scaled to force the data readout.

The veto signal is produced as logical OR of the total dead time of the data readout, the QDC busy and the trigger itself. The length of each of these signals including the total veto is measured for every trigger that occured.




Inputs:

Port : Channel

Signal

Used for

A
(ECL or LVDS)

0 TDT Total dead time
1 not used  
... ...  
31 not used  

B
(ECL or LVDS)

0 not used  
... ...  
31 not used  

D
(NIM)

0 PMT1 Plastic, Base a
1 PMT2 Plastic, Base b
2 not used  
... ...  
6 not used  
7 qdc_busy QDC busy




Outputs:

Port : Channel

Signal

Used for

E

(NIM)

0 not used  
1 QDC_gate QDC gate
2 not used  
3 not used  
4 trigger TDC input
5 veto TDC input
6 not veto TDC input
7 TDC_TRG TDC input
F

(ECL)

0 downscaled trigger T1
1 veto Scaler Control input 4
2 TDC_TRG TDC trigger
3    
4 PMT1  
5 PMT2  
6 pl_coin  
7 trigger_raw  
8 trigger  
9 QDC gate  
10 veto  
11 "vetosca_LNE"  
12 "mult_win"  
13 "vetosca_res"  
14 trigger_ds  
15 TDC_TRG  
16 PMT1 Scaler input
17 PMT2 Scaler input 
18 pl_coin Scaler input
19 trigger_raw  Scaler input
20 trigger  Scaler input
21 trigger_ds  Scaler input
22 LCLK  Scaler input
23 LCLK and veto  Scaler input
24 LCLK and not veto  Scaler input
25 not used  Scaler input
... ...  ...
31 not used  Scaler input
G

(NIM)

0 Trigger Monitoring
1 Dead Time Monitoring




Address-Map of User Firmware

(all standard registers with address above BASE + 0x7ffc are still available):

Address

BASE +

Register / Content

Data Access

Default Value

Bit range

comment

0x1018 A Mask D32 R/W 0xFFFFFFFF 31 ... 0 enables channels A:31..00 bit = 0: channel disabled
bit = 1: channel enabled
0x101C B Mask D32 R/W 0xFFFFFFFF 31 ... 0 enables channels B:31..00
0x1020 C Mask D32 R/W 0xFFFFFFFF 31 ... 0 enables channels C:31..00
0x1024 D Mask D32 R/W 0xFFFFFFFF 31 ... 0 enables channels D:31..00
0x1028 E Mask D32 R/W 0xFFFFFFFF 31 ... 0 enables channels E:31..00
0x102C F Mask D32 R/W 0xFFFFFFFF 31 ... 0 enables channels F:31..00
0x1030 ID Mezzanine D D32 R   2 ... 0 Port D bit 2..0: type of mezzanine board:
b000: A395A
b001: A395B
b010: A395C
b011: A395D
0x1034 ID Mezzanine E D32 R   2 ... 0 Port E
0x1038 ID Mezzanine F D32 R   2 ... 0 Port F
0x1100 User FPGA firmware revision D32 R   15 ... 0
bit 15..12: setup ID (0 = inel., 1 = transm.)
bit 11..8: major revision no.
bit 7..0: minor revision no.
0x1104 Scratch register D32 R/W 0xDEADBEEF 31 ... 0  
0x1108 LED control D32 R/W 0 8, 1, 0
bit 8: 0 = FPGA controled, 1 = user controled
bit 1: 0 = off, 1 = green
bit 0: 0 = off, 1 = red
0x110C GEO address D32 R/W 0 4 ... 0  
0x1110 Control register D32 R/W 0 10,8,4,3,2,0
bit 10: enable trigger production
bit 8: enable veto scaler
bit 4: input logic: 0 = AND, 1 = OR
bit 3: 1 = clear FIFO
bit 2: 1 = reset downscale counter
bit 0: 1 = reset veto length scaler
0x1114 Trigger Gate D32 R/W 0x00320032 31 ... 0
bit 31..16: delay
bit 15..0: width
in units of 10 ns
0x1118 QDC Gate D32 R/W 0x00320032 31 ... 0
0x1120 Trigger Downscale Factor D32 R/W 0x01010101 15 ... 0  
0x1300 FIFO status D32 R   19 ... 16, 12 ... 0
bit 19: almost empty (< 4000 words)
bit 18: almost full ( > 4000)
bit 17: empty
bit 16: full
bit 12..0: number of words stored
0x2000 FIFO data D32 R   31 ... 0  

Contact

Dr. Roland Beyer
PostDoc / Beamline scientist
Nuclear Physics
roland.beyerAthzdr.de
Phone: +49 351 260 - 3281

Mathias Kempe
student research assistant
Nuclear Physics