Contact

Dr. Roland Beyer
PostDoc / Beamline scientist
Nuclear Physics
roland.beyerAthzdr.de
Phone: +49 351 260 - 3281

Initialization of the VME electronics for (n,tot) experiments

(back to setup selection)

The initialization of the VME modules is controlled via the files "setup.ini". Each line of this file has to have the following structure: "variable = value". Everything behind an double slash "//" is interpreted as a comment. Values can be set decimal or hexadecimal (0x...). Tabs, multiple spaces and empty lines are ignored. A line containing "endnow = 1" will cause MBS to stop reading the setup file, i.e. everything below this line will be ignored.

The following variables are accepted:

setup.ini:

Variable

Meaning

Value Range

Recommended for (n,tot)

trigger
matching

stop
during
readout

trigger
matching

no stop
during
readout
continuous
storage
General
comment defines which comments should be printed out to the mbsprint_vme_0.l log-file 0: no comments
1: scaler values, errors, initialization
2: data readout information
3: even data send information
1
testrun defines if the current setup_vme_0.ini will be copied for logging into the directory "mbsrun/nng/log/" 0: setup will be saved
1: setup will not be saved
0
scalerrestart defines if a check should be enabled at each scaler readout (trigger type 2) if the electronics setup is paralyzed, i.e. if the QDC buffers are full although TDC almost full level not reached 0: disabled
1: enabled
1
fastanalysis defines if a fast analysis of the plastics time-of-flight spectra is written to "mbs_ratios.l" 0: disabled
1: enabled
1 1 0
printscaler defines if scaler values are printed out 0: disabled
1: enabled
1
bma_readout defined if data is read in block mode readout BMA (Note: MBS has to be compile with the "#define BMAREADOUT" to use this option) 0: disabled
1: enabled
0
print_qdc_error defines if errors of the QDC are printed out 0: disabled
1: enabled
1
print_tdc_error defines if errors of the TDC are printed out 0: disabled
1: enabled
1
Scaler
sis3820_LNEtime time between each scaler readout in seconds 1...420 15
Absorber
moveabsorber defines if the absorber is moved by software (if set to 0 changeabsorberauto, setabsorber and abschangetime# are meaningless) 0: disabled
1: enabled
1
changeabsorberauto defines if the absorber is changed automatically acording to the setting of absorber_order and abschangetime# 0: disabled
1: enabled
1
setabsorber absorber to be set if changeabsorberauto was set to 0 1...5 1
absorber_order sequence of absorber movements periodically passed sequence of 1...5 232425
abschangetime# time in s how long absorber # is in the beam, # = {1...5}   300
QDC
v965a_bset2 Bit set/clear 2 register (see manual, bits set to 1 are set, bits set to 0 are cleared)   0x5898 0x4898 0x4898
v985a_iped Iped value (see manual) >60 80
v965a_ch_ena_high enable pattern high gain channels   0x03
v965a_ch_ena_low enable pattern low gain channels   0x03
v965a_ch_thr_#_high high gain threshold of channel #, # = {0...7}   1
v965a_ch_thr_#_low low gain threshold of channel #, # = {0...7}   1
TDC
v1290n_ctrl control register (see manual)   0x0228
v1290n_alm_full Almost Full level 1... 32735 15000
v1290n_pout POUT output 0: Data Ready, 1: Full
2: Almost Full, 3: Error
2
v1290n_acqmode acquisition mode 0x0000: trigger matching
0x0100: continuous storage
0x0000 0x0000 0x0100
v1290n_winwidth match window width in ns 25...102375 6000
v1290n_winoff match window offset before trigger in ns -1000...51200 5000
v1290n_extrasearch extra search margin   200
v1290n_reject reject margin   100
v1290n_subtr_mode enable/disable trigger time subtraction 0x1400: enable
0x1500: disable
0x1400
v1290n_edgedet edge detection mode 0: pair
1: trailing
2: leading
3: leading + trailing
2
v1290n_leadres resolution for leading edge in ps   25
v1290n_widthres resolution for width in ps   100
v1290n_headtrail define if TDC header and trailer are enabled 0x3000: enabled
0x3100 disabled
0x3100
v1290n_enable input  channel enable pattern   0x5555
v1290n_extra_words number of words to read additionally to alm_full (ntot_cont only!)   not available 800
v1290n_read_all define if buffer is read completely up to first not valid data word (ntot_cont only!) 1: enable
2: disable
not available 1
Fast analysis
backmin ToF cuts: plastic background lower limit   see TDCSUM2BIN histogram
backmax ToF cuts: plastic background upper limit   see TDCSUM2BIN histogram
gamma1min ToF cuts: plastic gamma pre peak lower limit   see TDCSUM2BIN histogram
gamma1max ToF cuts: plastic gamma pre preak upper limit   see TDCSUM2BIN histogram
gamma2min ToF cuts: plastic gamma main peak lower limit   see TDCSUM2BIN histogram
gamma2max ToF cuts: plastic gamma main peak upper limit   see TDCSUM2BIN histogram
neutronmin ToF cuts: plastic neutrons lower limit   see TDCSUM2BIN histogram
neutronmax ToF cuts: plastic neutrons upper limit   see TDCSUM2BIN histogram
FPGA 1
v1495_reload defines if the V1495 user FPGA firmware is reloaded before initialization 0: disabled
1: enabled
0
v1495_a_mask_l Port A masking, low bits A[0] ... A[15] (see here) with TDT: 0x0001
without TDT: 0x0000
0x0001 0x0000 0x0000
v1495_a_mask_h Port A masking, high bits A[16] ... A[31]   0x0000
v1495_b_mask_l Port B masking, low bits B[0] ... B[15]   0x0000
v1495_b_mask_h Port B masking, high bits B[16] ... B[31]   0x0000
v1495_d_mask_l Port D masking, low bits D[0] ... D[15] (see here) with QDC busy: 0x0083
without QDC busy: 0x0003
0x0083 0x0003 0x0003
v1495_d_mask_h Port D masking, high bits D[16] ... D[31]   0x0000
v1495_e_mask_l Port E masking, low bits E[0] ... E[15] (see here)   0x00f2
v1495_e_mask_h Port E masking, high bits E[16] ... E[31]   0x0000
v1495_f_mask_l Port F masking, low bits F[0] ... F[15] (see here)   0xFFFF 0xFFFF 0xFFFA
v1495_f_mask_h Port F masking, high bits F[16] ... F[31] (see here)   0xFFFF
v1495_pl_logic defines the logic function to be applied to both inputs of the plastic detector 0: AND
1: OR
0
v1495_trig_wdth trigger width in ns (10 ns steps) 10...655350 3000
v1495_trig_delay TDC trigger delay in ns (10 ns steps) 10...655350 1000
v1495_delay QDC gate output delay in ns (10 ns steps) 10...655350 90
v1495_gate QDC gate output width in ns (10 ns steps) 10...655350 150
v1495_trig_scal downscale factor for readout Trigger 1...65535 31  1024 1024
FPGA 2
v1495_abs_reload defines if the V1495 user FPGA firmware is reloaded before initialization 0: disabled
1: enabled
0
v1495_abs_a_mask_l Port A masking, low bits A[0] ... A[15]   0x0000
v1495_abs_a_mask_h Port A masking, high bits A[16] ... A[31]   0x0000
v1495_abs_b_mask_l Port B masking, low bits B[0] ... B[15]   0x0000
v1495_abs_b_mask_h Port B masking, high bits B[16] ... B[31]   0x0000
v1495_abs_d_mask_l Port D masking, low bits D[0] ... D[15] (see here)   0x001F
v1495_abs_d_mask_h Port D masking, high bits D[16] ... D[31]   0x0000
v1495_abs_e_mask_l Port E masking, low bits E[0] ... E[15] (see here)   0x009F
v1495_abs_e_mask_h Port E masking, high bits E[16] ... E[31]   0x0000
v1495_abs_f_mask_l Port F masking, low bits F[0] ... F[15] (see here)   0x0003
v1495_abs_f_mask_h Port F masking, high bits F[16] ... F[31]   0x0000

Contact

Dr. Roland Beyer
PostDoc / Beamline scientist
Nuclear Physics
roland.beyerAthzdr.de
Phone: +49 351 260 - 3281