Characterisation of top-down fabricated NixSiy-Si hetrostructure undoped nanowires


Characterisation of top-down fabricated NixSiy-Si hetrostructure undoped nanowires

Deb, D.; Loffler, M.; Khan, M. B.; Georgiev, Y. M.; Erbe, A.

Semiconductor industry reaches the end of physical scaling soon and it is expected that future development will be based on new concepts: (i) new materials (high-mobility channel materials accompanied by metal gates with high-k gate dielectrics), (ii) new architectures (e.g. 3D integration), (iii) new functionality (e.g. reconfigurability), (iv) new computation principles (e.g. spintronics, quantum computing), etc [1]. In our work we focus on new functionality, specifically reconfigurable logic. The most promising industry compatible hardware for this logic is silicon nanowire based Schottky junction FET [2]. However, NiSi2-Si Schottky junctions in axial heterostructures (metal/intrinsic silicon/metal) are still complex and detailed studies of these structures are essential.
We report on heterostructure (NixSiy-Si) characterisation of reconfigurable, undoped silicon nanowire Schottky junction FETs. The nanowires are fabricated on silicon on insulator (SOI) substrates by electron beam lithography (EBL) using hydrogen silsesquioxane (HSQ), a negative-tone electron beam resist, followed by inductively-coupled plasma (ICP) etching. We produced silicon nanowires of 20 nm width and arrays of them with a pitch of ≈ 200 nm. Nickel was sputtered on the Si nanowires at lithographically defined areas followed by thermal annealing to create nickel-silicide Schottky junctions inside the nanowires, which also act as source-drain contacts. Silicidation was done on single nanowires and nanowire arrays with varying cross-sections and also for different annealing times.
We investigated the corresponding devices using SEM and TEM concerning their morphology and silicidation and determined the necessary parameters to allow for a reproducible scaling of these structures.
Furthermore, some cross-sections of nanowire samples were prepared by the standard FIB technique followed by low voltage FIB cleaning to preserve the crystal structure. We observed that the interface between the Ni silicide and the intrinsic silicon forms {111} facets. In contrast to common expectations, also features such as grain boundaries, nanotwins and multiple silicide phases between the Ni source and the Si part of the nanowire have been observed. Those features pose a technological challenge towards large-scale integration in future reconfigurable semiconductor devices and need to be properly studied and taken into account.
[1] L. Risch, Solid-State Electronics. 50 (2006) 527-535.
[2] A. Heinzig, T. Mikolajick, J. Trommer, D. Grimm and W. M. Weber, Nano Lett. 13 (2013) 4176-4181.

Keywords: Nanowires; TEM; silicon on insulator; Schottky junction; FETs; Silicidation

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