Ion Beam-Enabled CMOS-Compatible Manufacturing of SETs Operating at Room Temperature


Ion Beam-Enabled CMOS-Compatible Manufacturing of SETs Operating at Room Temperature

Facsko, S.; Heinig, K. H.; Stegemann, K. H.; Pruefer, T.; Xu, X.; Hlawacek, G.; Huebner, R.; Wolf, D.; Bischoff, L.; Moeller, W.; von Borany, J.

Electronics has been dominated by silicon since half a century. Si will dominate electronics another decade, however its functionality might change from classical field-controlled currents through channels (the Field Effect Transistor FET) to quantum mechanical effects like field-controlled hopping of single electrons from a source to a drain via a quantum dot (the Single Electron Transistor SET). Due to single electron hopping, the SET is the champion of low-power consumption. This is very attractive for the expanding Internet of Things (IoT): more and more devices need batteries and plugs. Therefore, together with improved batteries, advanced computation and communication must be delivered at extremely low-power consumption. At very low temperatures, the perfect functionality of SETs has been proven for tiny metal dots [1] and larger Si islands [2]. However, large-scale use of SETs requires Room Temperature (RT) operation, which can be achieved with tiny Si dots (<4 nm) in SiO2, exactly located between source and drain with distances of ~1…2 nm allowing quantum mechanical tunneling. Manufacturability of such nanostructures is the roadblock for large-scale use of SETs. Lithography cannot deliver the feature sizes of 1…3 nm required for RT operation. Therefore, there are currently intense studies to fulfill these requirements by self-organization processes. Convincing proof of concepts have been reported [see, e.g., 3] on room temperature operation of silicon based SETs. However, the self-organization processes developed so far are not reliable enough for large-scale integration.
The ion beam technique is a well-established technology in microelectronics used for doping and amorphization of semiconductors and even for ion beam synthesis of buried layers. The parameters of ion beam processing like ion flux, fluence and energy as well as the temperature and time of the subsequent thermal treatment are very well controllable. Therefore we searched for a self-organization process based on ion irradiation which overcomes the bottleneck of manufacturability of SETs working at room temperature.
Thus, in the framework of an international project funded by the European Commission [4], we develop an ion-assisted, CMOS-compatible process [4] which will provide both (i) self-assembly of a single Si dot and (ii) its self-alignment with source and drain.
Based on our knowledge of ion implantation [5,6] and irradiation [7] induced phase separation and Ostwald ripening processes as well as ion-assisted fabrication of non-volatile nanocluster memories [8], we concluded by computer simulations that phase separation of tiny, metastable SiOx volumes (<103 nm3) will transiently lead to a single Si nanodot in SiO2 (see Fig.2).
The tiny, metastable SiOx volume is formed by ion beam mixing of a bulk Si/SiO2/a-Si layer stack. In order to get the very small SiOx volume necessary for single dot formation, two approaches are used: (i) point-like Ne+ irradiation for fundamental studies, and (ii) broad beam Si+ irradiation of nanopillars for the device fabrication (see Fig. 3).
For both approaches, the predictive computer simulations use for the dynamical 3D ion beam mixing the recently developed program TRI3DYN [9]. TRI3DYN provides the initial conditions for phase separation and coarsening processes simulated (see, e.g. Fig. 2) with the 3D kinetic Monte Carlo program 3DkMC [6].
First results of our studies with the Helium Ion Microscope are shown in Figs. 4 and 5. The ion beam mixing of the SiO2 layer as imaged by EFTEM agrees nicely with that predicted by TRI3DYN simulations. Using this mixing profile as input for 3DkMC simulations, a single Si nanocluster is formed (Fig. 4). Although it appears to be extremely difficult to image a single Si nanodot of 2…3 nm diameter embedded in SiO2 in a ~50 nm thick TEM lamella, Fig 5 proves that after annealing such a single cluster can be formed. The next activities will be focused on the single Si nanodot fabrication in Si nanopillars and the optimization of this process for RT-SET fabrication.

This work has been funded by the European Union’s Horizon 2020 research and innovation program under grant agreement No 688072.

1. K. Maeda et al., ACS Nano (2012) 2798.
2. S. Ihara et al., Appl. Phys. Lett. 107 (2015) 13102. SET in SOI
3. V. Deshpande et al., Proc. of the IEDM12-Conf. (2012) 195.
4. Research Project IONS4SET funded by the European Commission
5. M. Strobel et al., NIM B147 (1999) 343.
6. M. Strobel, K.-H. Heinig, W. Möller, Phys. Rev. B64 (2001) 245422.
7. K.H. Heinig, T. Müller, B. Schmidt, M. Strobel, W. Möller, Appl. Phys. A77 (2003) 17.
8. T. Mueller et al., Appl .Phys. Lett. 81 (2002) 3049; ibid 85 (2004) 2373.
9. W. Möller, NIM B322 (2014) 23.

Keywords: ion irradiation; self-assembly; Si nanocrystals; single electron transistor

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