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Analysis of NixSiy-Si Nanowires for Next Generation Electronics
Loffler, M.; Deb, D.; Muhle, U.;
Si Nanowires are one of the foremost candidates for “beyond CMOS” technology, both from the point of miniaturization (more Moore) but also from the point of added function (more-than-Moore). NiSi2-Si Schottky junctions in nanowires are the building blocks for the design of reconfigurable logic on the hardware level [1]. However, the device parameters depend very sensitively on the geometry of the interface and the transistor makeup.
Here we present the analysis of NixSiy-Si nanowires fabricated on silicon-on-insulator (SOI) substrate using a top-down approach and silicidized using thermal Ni diffusion from lithographically patterned electrodes. We employed both SEM and TEM techniques to identify regions of interest to be prepared by the standard FIB technique followed by 1kV FIB cleaning to preserve the crystal structure.
We observed that the interface forms {111} facets (Figure 1). Furthermore, we observed grain boundaries, nanotwins and multiple silicide phases between the Ni source and the Si part of the nanowire.
Keywords: TEM, RFETs, Nanaowires
  • Poster
    Scandem 2016, 07.-10.06.2016, Trondheim, Norway

Publ.-Id: 25031 - Permalink