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Towards Scalable Reconfigurable Field Effect Transistor using Flash Lamp Annealing

Khan, M. B.; Ghosh, S.; Prucnal, S.; Mauersberger, T.; Hübner, R.; Simon, M.; Mikolajick, T.; Erbe, A.; Georgiev, Y.

Introduction: For decades the miniaturization of logic circuitry was a result of down scaling of the field effect transistor (FET). This scaling has reached its end and, therefore, new device materials and concepts have been under research for the last years. One approach is to increase the functionality of an individual device rather than scaling down its size. Such a device concept is the reconfigurable FET (RFET), which can be configured to n- or p-polarity dynamically [1].
RFETs are based on Schottky barrier FETs and feature an intrinsic Si nanowire (NW) channel. The Schottky junctions are formed by placing Nickel (Ni) contacts on both ends of the NW and conductive Ni-silicide segments are formed in the NW by an annealing process. In RFETs, two gates are usually placed on top of these Schottky junctions and by the application of electrostatic potential at the gates unipolar n- or p-transport is tuned in the channel. There are several Ni-silicide phases out of which NiSi2 is preferred as it yields sharp NiSi2-Si junctions. Moreover, its metal work function is near the mid bandgap of Si. This enables tuning the RFET to n- or p-transport by respectively bending the bands when applying electrostatic potential at the gates (Fig. 1).
Top-down fabrication of Schottky barrier FETs is a pre-requisite for the large-scale integration of RFETs. The challenges in this fabrication process include proper patterning of NWs, obtaining symmetric p- and n-currents and the scalability of the devices. The first two tasks have been solved as reported in [2]. However, the lack of controllable intrusion of silicide into the NWs remains an obstacle for device scalability [3-5]. Here we report that a silicidation process based on millisecond flash lamp annealing (FLA) significantly improves the uniformity of silicide intrusion at the two ends of the NWs. Such a gain in silicidation control will decisively allow creating RFETs with short channel lengths.
Fabrication: The devices are fabricated on silicon-on-insulator (SOI) substrates with 20 nm undoped top Si layer and 102 nm buried oxide. Electron beam lithography (EBL) and dry etching are used to fabricate NWs with 20 nm width as described in [3]. NWs are oxidized with a rapid thermal process and a ~6 nm thick SiO2 shell is formed to passivate NW surface. After wet etching SiO2 from desired areas, Ni contacts are placed in those areas using EBL and Ni evaporation. FLA is used for silicidation of the NWs and the results show equally long silicide intrusions (Fig. 2).
Results: The FLA process time is much shorter (0.5-20 ms) compared to conventional rapid thermal annealing (RTA) [6]. FLA based silicidation process is developed which, unlike previously reported RTA based processes, can deliver scalable RFETs. High resolution TEM (HRTEM) shows the formation of the desired NiSi2 phase and atomically abrupt Schottky junctions (Fig. 4). This is also confirmed by element mapping based on energy dispersive X-ray spectroscopy (EDXS) (Fig. 3). The transfer characteristics of the device with back-gate operation show an ambipolar behavior with an ON/OFF ratio of 9 orders of magnitude (Fig. 5). The gate voltage (VBG) was swept from -30 V to 30 V and the drain to source voltage (VD) was varied from 0.25 V to 0.75 V. The unipolar behavior can be tuned by fabricating two or more top gates. This will also reduce the additional hysteresis caused by using the buried oxide as a very thick gate dielectric.
Applications: The FLA-based silicidation process enables channel scaling. Devices based on this process show promising results and have potential applications as devices with reduced power consumption and low chip area [7]. These RFETs can also be used for the fabrication of power-efficient multi-independent gate-based logic circuits [8]. Moreover, the number of transistors and the chip area consumption can be reduced with the help of these transistors, preserving at the same time the functionality of the integrated circuits [9].
1.Heinzig, A. et al., Nano Lett., 2011.12(1):pp.119-124. 2.Simon, M. et al.,IEEE Trans Nanotechnol, 2017.16(5):pp.812-819.
3.Khan, B.M. et al., Appl. Sci. 2019. 9(17),3462. 4.Habicht, S. et al., Nanotechnology, 2010. 21(10): pp.105701.
5.Ogata, K. et al., Nanotechnology,2011.22(36):pp.365305. 6.Rebohle, L. et al., Semicond Sci Technol, 2016. 31(10): pp.103001.
7.Gaillardon, P.E. at al., in LATS, 2016, pp.195-200. 8.Rai, S. et al., IEEE Transactions VLSI, 2019.27(3):pp.560-572.
9.Raitza, M., et al., in DATE.2017,pp.338-343.

  • Contribution to proceedings
    2020 Device Research Conference (DRC), 21.-24.06.2020, Columbus, OH, USA

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Publ.-Id: 32236