Publications Repository - Helmholtz-Zentrum Dresden-Rossendorf

1 Publication

Challenges to TEM sample preparation of stacked Si/SiO2/Si nanopillars for SETs using Focused Ion Beam

Engelmann, H.-J.; Bischoff, L.; Hübner, R.; Heinig, K.-H.; Hlawacek, G.; Borany, J.; Pourteau, M. L.; Rademaker, G.

Single Electron Transistors (SETs) open the way to semiconductor devices with extremely low power consumption. Quantum mechanical effects are used in such transistors: field-controlled tunneling of single electrons from a source to a drain via a quantum dot. SETs can be manufactured as thin Si pillars (source and drain) with a Si oxide layer in-between containing one Si quantum dot (Fig. 1). After SiOx formation by ion beam mixing, a thermally activated phase separation including Ostwald ripening results in a self-organization of Si nanocrystals in the SiO2 layer acting as Si quantum dots (Si NDs). For SET operation at room temperature, the diameter of the Si pillars needs to be < 12 nm, the Si ND diameter must be in the range of 2…3 nm and the distances between Si NDs and source/drain cannot be larger than 1.5 nm allowing quantum mechanical tunneling of the electrons.
Thus, Transmission Electron Microscopy (TEM) must be used for the structural characterization of these SETs. Si NDs inside the SiO2 matrix can only be detected by using the Si plasmon loss in the energy-filtered TEM mode. TEM sample preparation is challenging because of the very small 3D structure of the pillars (Fig.2) and the need for very thin TEM lamellae (30…40 nm in thickness). The Focused Ion Beam (FIB) lift-out technique can be used to prepare such samples. Setting markers and gradual thinning of the lamella from both sides (with TEM inspection in between) is necessary.
Surprisingly, comprehensive TEM studies uncovered that the oxide layer of a Si/ SiO2/Si layer stack can become dramatically thinner in pillars fabricated from this stack by Reactive Ion Etching (RIE). The oxide layer thinning depends on the pillar diameter. For instance, an originally 8 nm thick SiO2 layer is reduced to 2.6 nm in 15 nm diameter pillars. In order to prove that this oxide shrinkage is caused by RIE and not by sample preparation the most critical process in the FIB preparation - which is the electron-beam-assisted carbon-protection-layer deposition - was analyzed in detail: pillars were irradiated with different electron doses and then, the SiO2 thickness was measured in the TEM. As can be seen in Fig. 3 there is a clear influence of the electron dose on the oxide thickness. This can be explained by charge accumulation in pillar Si caps (drain), followed by dielectric breakdowns through filament formation across the SiO2 layer accompanied by Si oxide dissociation and oxygen emanation from the SiO2 disc rim of the pillars. However, as can be seen in Fig. 3 the FIB-caused contribution to the oxide thickness reduction is only a small part. The main contribution comes from the pillar RIE process based on the same physical reason (charging of the pillar Si caps).
This work was supported by the European Union’s H-2020 research project ‘IONS4SET’ under Grant Agreement No. 688072

Keywords: Single Electron Transistor (SET); Structural Characterization; Plasmon Loss Energy-Filtered TEM; TEM Sample Preparation; Focused Ion Beam; Si Oxide Layer Thickness Reduction

  • Lecture (Conference) (Online presentation)
    FIT4NANO/Eu-F-N workshop, 27.-30.09.2021, Wien, Österreich

Permalink: https://www.hzdr.de/publications/Publ-33200
Publ.-Id: 33200