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Towards a Vertical Nanopillar-Based Single Electron Transistor – A High-Temperature Ion Beam Irradiation Approach
Xu, X.ORC; Heinig, K.; Möller, W.; Gharbi, A.; Tiron, R.; Engelmann, H.; Bischoff, L.; Prüfer, T.; Hübner, R.; Facsko, S.; Hlawacek, G.; von Borany, J.
We propose an ion irradiation based method to fabricate a single Si nanocrystal embedded in a Si(001)/SiO2/Si nanopillar layer stack as a prerequisite for manufacturing a CMOS-compatible, room-temperature Si single electron transistor. After either 50 keV broad beam Si+ or 25 keV focused Ne+ beam from a helium ion microscope (HIM) irradiation of the nanopillars (with diameter of 35 nm and height of 70 nm) at room temperature with a medium fluence (2e16 ions/cm2), strong plastic deformation has been observed which hinders further device integration. This differs from predictions made by the Monte-Carlo based simulations using the program TRI3DYN. We assume that it is the result from the ion beam induced amophisation of Si accompanied by the ion hammering effect. The amorphous nano-structure behaves viscously and the surface capillary force dictates the final shape. To confirm such a theory, ion irradiation at elevated temperatures (up to 672 K) has been performed and no plastic deformation was observed under these conditions. Bright-field transmission electron microscopy micrographs confirmed the crystallinity of the substrate and nanopillars after HT-irradiation.
When a semiconductor material such as silicon is heated above its amorphisation critical temperature during ion irradiation, it stays crystalline due to an interplay between ion damage and dynamic annealing process. Viscous flow does not occur for the crystalline nano-structures and the shape remains intact. This effect has been observed previously mainly for swift heavy ions and energies higher than 100 keV. Such high-temperature irradiation, when carried out on a nanopillar with Si/SiO2/Si layer stack, would induce ion beam mixing without suffering from the plastic deformation of the nanostructure. Due to a limited mixing volume, single Si-NCs would form in a subsequent rapid thermal annealing process via Oswald ripening and serve as a basic structure of a gate-all-around single electron transistor device.
This work is supported by the European Union’s H-2020 research project ‘IONS4SET’ under Grant Agreement No. 688072.
  • Lecture (Conference)
    2018 MRS Fall Meeting & Exhibit, 25.11.2018, Boston, USA

Publ.-Id: 28563 - Permalink