CMOS compatible bottom-up approach of multi-dot floating-gate nonvolatile memory fabrication.

CMOS compatible bottom-up approach of multi-dot floating-gate nonvolatile memory fabrication.

Heinig, K.-H.; Schmidt, B.; Mueller, T.; Roentzsch, L.; Stegemann, K.-H.

Scalability and performance of current FLASH memories could be improved substantially by novel devices based on multi-dot floating gate MOSFETS. Until today, ten years of research effort have been devoted to Tiwari`s idea [1] to replace the poly-silicon floating-gate of FLASH memories by a layer of Si nanocrystals. Although several groups and companies developed test-devices, a breakthrough was not achieved due to two main reasons: (i) The CMOS compatible fabrication of the layer of nanocrystals remains a great challenge (monolayer of monodisperse Si nanocrystals of high density, which has to be embedded in the gate oxide at a controlled tunnel distance of a few nm above the Si channel). (ii) The retention of the test-devices did not reach the industrial standard. Here, we present a CMOS compatible bottom-up approach of a multi-dot floating-gate nonvolatile memory fabrication which is based on ion-beam mixing of Si-SiO2 interfaces [2]. By energetic Si ion irradiation through the poly-Si gate and the gate oxide into the Si substrate, a SiOx layer forms in the interface region. During post-irradiation annealing, the flat Si/SiO2 interface rebuilts rapidly by spinodal decomposition and interface area minimization. However, in the tail of the mixing profile, Si excess nucleates in the gate oxide layer forming Si nanocrystals. These nanocrystals are separated from the substrate by a few nm thin SiO2 layer which is free of Si excess. Experimental and atomistic computer simulation studies of this bottom-up approach will be presented. Electrical characteristics of devices, which were fabricated in an industrial environment, will be shown. Predictions to overcome the main drawback in view of applicability as memory devices, i.e. the data retention of only a few months at room temperature, will be discussed.
[ 1] S. Tiwari et al., IEEE Int. Electron Devices Meeting Technical Digest, 521–524 (1995).
[ 2] K.-H. Heinig, T. Müller, B.Schmidt, M. Strobel, W. Möller, Appl. Phys. A 77, 17–25 (2003).

Keywords: nanostructures; silicon; silica; ion-irradiation; self-organization; FLASH memory; modeling; process simulation

  • Lecture (Conference)
    MRS Spring Meeting 2006, Symposium "Science and Technology of Nonvolatile Memories", 17.-21.04.2006, San Francisco, USA

Publ.-Id: 9282