III-V Nanostructures in Silicon
The downscaling and stressor technology of Si based devices is extending the performance of the silicon channel to its limits. One solution for the performance progress which can overcome the downsizing limit in silicon technology is the integration of different functional optoelectronic elements within one chip. Moreover, the power consumption of the microprocessors can be significantly reduced using photons instead of electrons for computer chip communication. As non-silicon transistor channel materials for future high-speed and low power logic CMOS applications III-V compound semiconductors have a huge potential. The remaining open question is which technology integrating III-V compound semiconductors with silicon will be used.
We propose to realize a compact, CMOS compatible and fully integrated solution for the integration of III-V compound semiconductors with silicon technology for optoelectronic applications. The III-V nanostructured semiconductors (InAs, GaAs or InP) are synthesized in either silicon or SOI wafers using the combined ion implantation and millisecond flash lamp annealing (FLA) techniques.
Fig. 1. Schematic overview of the integration of III-V compound semiconductors in SOI wafers and SEM image of implanted, annealed and etched sample containing InAs QDs.
Based on sequential ion implantation, post-implantation millisecond range FLA and selective chemical etching (Fig. 1), high quality heterojunction consisting of InAs or InP single-crystal nanodots on silicon fingers have been obtained (see Fig. 2).
Fig. 2. Semilogarithmic I-V characteristic of an n-InAs/p-Si heterojunction at room temperature on a semilogarithmic scale (a). The inset displays the topography of the surface. The HRTEM image in (b) shows the structure of such a heterojunction.
Silicon-on-insulator is one of the most advanced Si-based materials for high performance devices and integrated circuits. SOI wafers with 90 nm p-type silicon on 140 nm SiO2 were implanted with In and As or In and P ions to obtained InAs or InP QDs, respectively. The data obtained by µ-Raman spectroscopy (Fig. 3) directly confirms the (111) oriented crystalline III-V nanostructures formation on SOI wafers.The use of a mask layer patterned by ebeam lithography allows the formation of quantum dots at defined positions (Fig. 4). Finally, this technique enables the formation of such a heterojunction in a nanowire (Fig. 5).
Fig. 3. µ-Raman spectra of a III-V nanostructure in SOI wafers consisting of InAs (a) and InP (b) crystals. The insets (a) and (b) show a cross-sectional TEM image of single InAs QDs and a SEM image of InP QDs with well-defined InP trenches, respectively.
Fig. 4. AFM topography of In and As implanted, annealed and selectively etched samples. The implantation area was 200×200 nm2 (a), 500×500 nm2 (b), 2000×100 nm2 (c) and 2000×400 nm2 (d). The indium spatial distribution obtained by µ-Auger spectroscopy and SEM image of InAs QD is shown in (e) and (f), respectively.
Fig. 5. Si nanowire with an InAs segment. The nanowire was grown via the VLS mechanism (vapor-liguid-solid growth mechanismus).