SPICE simulations of self-actuated piezoresistive cantilever arrays

A 2-dimensional massively parallel self-actuated piezoresistive cantilever arrays are a possible candidate for use in high speed AFM based surface imaging systems. By the utilization of cantilever arrays consisting of several hundred of cantilevers the AFM inspection speed of the next generations IC can be significantly increased. In the frame of the European Project PRONANO we are developing such arrays based on self-actuated piezoresistive cantilever. For design optimization and error detection in MEMS structures, which include a lot of CMOS processing, a device and process simulations are useful and essential. Besides the description of the electro-mechanic behaviour of the MEMS-part a parasitic effects (electrical crosstalk, noise, and temperature influence) of the CMOS have to be included. SPICE is well suitable tool for these investigations.
The investigated cantilever system consists of a p-doped piezoresistive sensor and a p-doped heater is represented qualitatively in Figure 2. The meander structure is the ion implanted heater to control the thermal bending of the silicon beam. An AC power supply is applied to the heater to bring the beam in resonant oscillation and to steer the position of the free end of the beam. The beam bending is determined with the piezoresistor. Experimentally a current crosstalk was detected. At the configuration a voltage peak occurs during the positive half wave of the sensor signal. The magnitude of this voltage peak depends on the dc-voltage of the heater signal. To simulate this effect a suitable equivalent network model was developed. The heater and the piezoresistor were modeled by resistor chains, which are interconnected to the n-doped silicon body (resistor network) by diodes including the junction capacitance. Additionally pnp-transistors were inserted in the equivalent circuit, where heater and piezoresistor are located near each other.
With this circuit model the experimentally determined behavior could be simulated and the effect could be explained as a current crosstalk across the parasitic transistors. We will show that this effect can be significantly suppressed by applying a certain substrate bias and corresponding design optimisation.