Electrical characterization of sub-20 nm silicon nanowires fabricated using electron beam lithography and inductively coupled plasma etching


Electrical characterization of sub-20 nm silicon nanowires fabricated using electron beam lithography and inductively coupled plasma etching

Khan, M. B.; Deb, D.; Georgiev, Y. M.; Erbe, A.

Scaling down of CMOS faces strong challenges due to which advanced fabrication techniques, advanced materials, new device and logic concepts have gained importance. These concepts include undoped silicon nanowire based reconfigurable devices, which can be programmed as p-FET or n-FET by controlling the electrostatic potential applied at gate electrodes. In this work, fabrication and electrical characterization of undoped sub-20 nm silicon nanowires (SiNWs) is reported. SiNWs are fabricated on intrinsic silicon-on-insulator (SOI) substrates in <110> and <100> crystal directions using a top down approach. Hydrogen silsesquioxane (HSQ), a negative tone electron beam resist, is used for nano-patterning and as a hard mask for etching. Nanowire etching process is optimized using an inductively coupled plasma (ICP) source and C4F8/SF6/O2 mixed gas recipe at 18 oC. These NWs are oxidized to form a SiO2 shell and subsequently silicidized. Final observations include different charge carrier transport in <110> and <100> crystal directions.

Keywords: Silicon nanowire; etching; lithography; schottky barrier devices

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Permalink: https://www.hzdr.de/publications/Publ-26880
Publ.-Id: 26880