Performance Enhancement of Reconfigurable Field Effect Transistors (RFETs)


Performance Enhancement of Reconfigurable Field Effect Transistors (RFETs)

Khan, M. B.; Deb, D.; Georgiev, Y. M.; Erbe, A.

Scaling down of CMOS faces strong challenges due to which advanced fabrication techniques, advanced materials, new device and logic concepts have gained importance. These concepts include undoped silicon nanowire based reconfigurable devices, which can be programmed as p- or n-channel FETs by controlling the electrostatic potential applied at gate electrodes. In this talk, fabrication and electrical characterization of undoped sub-20 nm silicon nanowires (SiNWs) will be reported. SiNWs are fabricated on intrinsic silicon-on-insulator (SOI) substrates in <110> and <100> crystal orientations using a top down approach. Hydrogen silsesquioxane (HSQ), a negative tone electron beam resist, is used for nano-patterning and as a hard mask for etching. Nanowire etching process is optimized using an inductively coupled plasma (ICP) source and C4F8/SF6/O2 mixed gas recipe at 18◦C. These NWs are subsequently silicidized to form Scottky junctions. Electrical characterization shows different charge carrier transport in <110> and <100> crystal orientations. Control over silicide formation to enhance the performance of these devices will be discussed.

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  • Lecture (Conference)
    IHRS NanoNet Annual Workshop 2017, 16.-18.08.2017, Klingenberg-Colmnitz, Germany

Permalink: https://www.hzdr.de/publications/Publ-26881
Publ.-Id: 26881