Organized Single Si Quantum Dots in tiny SiO2 volumes: Self-alignment for Single Electron Transistors

Room temperature (RT) operation of Single Electron Transistors (SETs) is based on two conditions: (i) The Coulomb blockade energy of charging a dot must be smaller than kT, i.e. a Si quantum dot must be <5nm. (ii) The electron tunneling distance from the Si dot embedded in SiO2 to an electrode must be <1.5nm. Such dimensions are beyond the limits of top-down processes like Electron Beam Lithography (EBL) and Reactive Ion Etching (RIE).
As we demonstrate by atomistic computer simulations, a functional nanostructure for RT-SETs can be achieved by bottom-up processes, self-organization and self-alignment: Phase separation in a tiny volume ~(10nm)3 of metastable SiOx results in the formation of a single Si precipitate in SiO2 . And, if this SiOx volume is bordered at two sides by an Si/SiOx interface, the Si dot becomes self-aligned (isolated) by an SiO2 layer (SiOx denuted by excess Si).
The tiny SiOx volume has been formed by top-down processes: From a bulk Si/7nm SiO2/a-Si layer stack nanopillars of <20nm diameter have been fabricated by EBL and RIE. Then, the SiO2 layer embedded in the nanopillar was transformed into SiOx by 50keV Si+ ion irradiation. During subsequent annealing the single Si dot is expected to form. Two nanoscale phenomena not observed so far have to be overcome to get a reliable RT-SET fabrication.
This work has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 688072.