Microstructure and electrical properties of gate-SiO\sub{2} containing Ge-nanoclusters for memory applications


Microstructure and electrical properties of gate-SiO\sub{2} containing Ge-nanoclusters for memory applications

Thees, H.-J.; Wittmaack, M.; Stegemann, K.-H.; von Borany, J.; Heinig, K.-H.; Gebel, T.

MOSFET´s with gateoxides containing nanoclusters (Si, Ge, Sn, Sb) fabricated with different techniques (implantation, LPCVD, sputtering) are a very promising approach for future memories. This contribution reports on results obtained on Ge-implanted MOS capacitors. By varying the implantation and annealing parameters the Ge depth profile and the cluster size and distribution can be controlled. The experimental results are explained by a theoretical model, which is based on TRIM calculations, rate-equation studies and 3D kinetic Monte Carlo simulations. The electrical properties of gate-SiO\sub{2} containing Ge-nanoclusters are investigated in detail with emphasis on its feasibility for memory applications.

Keywords: ion beam synthesis; nanoclusters; nonvolatile merory

  • Lecture (Conference)
    10th Workshop on Dielectrics in Microelectronics Barcelona, November 3-5, 1999
  • Microelectronics Reliability 40 (2000) 867-871

Permalink: https://www.hzdr.de/publications/Publ-2986
Publ.-Id: 2986