Towards a vertical nanopillar-based single electron transistor – a high-temperature ion beam irradiation approach

The usage of ion beam irradiation on vertical nanopillar structures is a prerequisite for fabricating a CMOS-compatible, vertical gate-all-around(GAA) SET device. After either 50 keV broad beam Si+ or 25 keV focused Ne+ beam from a helium ion microscope (HIM) irradiation of the nanopillars (with diameter of 35 nm and height of 70 nm) at room temperature with a medium fluence (2e16 ions/cm2), strong plastic deformation has been observed which hinders further device integration. This differs from predictions made by the Monte-Carlo based simulations using the program TRI3DYN. We assume that it is the result from the ion beam induced amorphization of Si accompanied by the ion hammering effect. The amorphous nano-structure behaves viscously and the surface capillary force dictates the final shape. To confirm such a theory, ion irradiation at elevated temperatures (up to 672 K) has been performed and no plastic deformation was observed under these conditions. Bright-field transmission electron microscopy micrographs as well as Electron Beam Diffraction confirmed the crystallinity of the substrate and nanopillars after HT-irradiation. In addition, a steady thinning process of the nanopillars to a diameter of 10 nm has been observed at higher fluencies. As the original pillar diameter is comparable to the size of the collision cascade, instead of direct knock-on sputtering, enhanced forward sputtering through the sidewalls of the pillar is responsible for this effect. The relation between ion beam energy, flux and temperature with the observed thinning of the nanopillars has been studied experimentally and compared to TRI3DYN simulations. Such a reliable and CMOS-compatible process could serve as a potential downscaling technique for large-scale fabrication of nanopillar-based electronics.