Flash Lamp Processing of III/V compound semiconductors on silicon and SOI wafers for functional photronic devices


Flash Lamp Processing of III/V compound semiconductors on silicon and SOI wafers for functional photronic devices

Prucnal, S.; Zuk, J.; Pyszniak, K.; Drozdziel, A.; Facsko, S.; Mücklich, A.; Zhou, S. Q.; Ou, X.; Liedke, M. O.; Liedke, B.; Turek, M.; Skorupa, W.

One of the solutions enabling performance progress, which can overcome the downsizing limit in silicon technology, is the integration of different functional optoelectronic devices within a single chip. Silicon with its indirect band gap has poor optical properties, which is its main drawback. Therefore, a different material has to be used for the on-chip optical interconnections, e.g. a direct band gap III-V compound semiconductor material. Recently we demonstrated a compact, CMOS compatible and fully integrated solution for the integration of III-V semiconductor nanocrystals with silicon technology for optoelectronic applications. They are synthesized in silicon using combined ion beam implantation and millisecond flash lamp annealing (FLA) techniques [NanoLett. 11, 2814 (2011)]. FLA appears to be the most suitable technique for this purpose. The energy budget introduced to the sample during FLA is sufficient to recrystallize silicon amorphized during the ion implantation and to form III-V nanocrystals (NCs) via the liquid phase. In this talk we will present results of the microstructural, optical and electrical properties of III-V quantum dots (InAs, GaAs and InP) formed in silicon or SOI wafers. An evolution of the III-V nanocrystals growth during FLA and the influence of the annealing parameters on the crystallographic orientation, shape and size will be explored. Moreover, the self-organization of the III-V nano-objects on the SOI wafers after flashing will be presented. A unique nano-swelling effect appearing during ion implantation of the SOI wafers combined with milliseconds range liquid phase epitaxy for the self-organization is responsible. Conventional selective etching was used to form the n-III-V/p-Si heterojunction. Current-voltage measurements confirm the heterojunction diode formation between n-type III-V quantum dots and p-type Si substrate. The main advantage of our method is its integration with large-scale silicon technology, which also allows applying it for Si-based photronic devices.

Keywords: III-V QDs; silicon; ion implantation; SOI; flash lamp annealing; heterojunction

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  • Invited lecture (Conferences)
    9th International Conference Ion implantation and other applications of ions and electrons, ION 2012, 25.-28.06.2012, Kazimierz Dolny, Poland

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