CMOS-compatible Single Si Quantum Dot fabrication in a SiO₂ layer sandwiched in a Si nanopillar for a Room Temperature Single Electron Transistor

Abstract :

The transistor pathway predicts an evolution from lateral MOSFETs via FinFETs to vertical nanowire gate-all-around FETs (vNW GAA-FET). Aiming at low-power electronics we replace the channel of the vNW GAA-FET by a SiO2 layer with an embedded Si Quantum Dot (QD), thus manufacturing a Single Electron Transistor (SET). To achieve room temperature (RT) operation of the vNW GAA-SET, Si QDs of ~3 nm diameter and tunneling distances of < 1 nm have to be manufactured. This is far beyond the present possibilities of lithography.
The challenge of such tiny structures has been solved in the framework of our European project IONS4SET [1] by means of a controlled self-organization and self-alignment process. Nanopillars with diameters down to ~20nm have been fabricated from Si/SiO2/Si layer stacks by Electron Beam Lithography and Reactive Ion Etching (RIE), a further diameter reduction to ~10nm has been achieved by sacrificial plasma oxidation. Before RIE the SiO2 layer is transferred to SiOx by Si+ ion beam mixing, which allows a controlled self-organization of a Si QD during thermally activated phase separation using RTA. During phase separation the Si QD becomes also self-aligned with respect of the upper and lower Si, thus forming the tunnel distances of ~1nm.
[1] This work has received funding from the European Unions Horizon 2020 research and innovation programme under grant agreement No 688072 (www.ions4set.eu).