Microstructural and electrical properties of SiO2 layers containing Ge and Si nanoclusters

In the last years nanoclusters attracted much attention because of their outstanding properties for the use in opto- and microelectronics. As an example nanocrystal memories are a promising approach towards new scalable non-volatile memory structures [1, 2]. Because of their low programming voltages and the direct tunneling process for charging they overcome limitations of currently used flash EEPROM technologies. The simple structure and the possible process integration with only a few more additional process steps make this type of memory a well-suited candidate for applications in embedded systems. An effective method of producing nanoclusters in SiO2 is ion beam synthesis using Ge - or Si - implantation and subsequent annealing. This method allows the precise control over the distribution as well as the number of implanted ions and complies with common silicon technology.
This work is focused on the comparison of the properties of Si and Ge nanoclusters prepared by ion beam synthesis. Thin SiO2 films (20 and 30 nm,) were thermally grown on n-type (100) Si) and implanted with Ge+ (12 and 20 keV) and Si+ (6 and 12 keV) ions. Subsequently rapid thermal annealing was performed at 950°C for 30 s under a nitrogen atmosphere. Following that a poly-Si layer (300 nm) was deposited by LPCVD and subsequently doped with P+ ions. The poly-Si layer was etched to form the gate electrode of a MOS capacitor and several additional thermal treatment steps were carried out.

Microstructural investigations (XTEM, RBS and XPS) of Ge clusters showed dependent on the experimental conditions either only one volume cluster band or a two band structure consisting of one cluster band near the interface SiO2/Si and one volume band. All clusters were found in the amorphous state. As an example for 30 nm SiO2 layers implanted with 20 keV Ge+ ions to a dose of 5x1015 cm-2 show a sharp cluster band with a cluster density of 3.5x1011 cm-2 ( 50 %) in a distance of about 3 nm to the interface Si / SiO2. This structure is therefore of large interest for memory applications.
The process leading to the formation of this interface cluster band is based on the dynamics of the ion implantation. A model based on TRIM calculations, rate equation studies and 3D - kinetic Monte Carlo simulations explains this self organization process [3]. Small Si agglomerates are formed during implantation due to collisional mixing and near interface oxygen diffusion. During the annealing process they act as nucleation centers and diffusing Ge from the implanted Ge maximum is trapped at these centers and forms clusters. As a result a sharp - like cluster band is formed.

Charge storage effects of the MOS capacitors have been studied through I-V and high frequency C-V measurements after FN stress. For Ge implanted layers, samples containing bulk and interface clusters show larger programming window sizes but worse retention characteristics than samples with bulk clusters only. This means, that direct tunneling leads to a faster discharging of the clusters near the interface.
Memory effects of Ge and Si nanocrystal based memory structures were reported to be similiar in Ref. [2]. In our work however the behavior of Ge and Si nanocluster based MOS-capacitors was found to be different. The programming window using 6 V / 100 ms pulses for Ge based structures is larger than that for Si (2.0 V vs. 0.2 V).
In Fig. 1 investigations of the retention characteristics are shown. The samples have been stressed with pulses of 15 V / 10 ms. After the stress the samples were stored at a temperature of 250°C to get information about long term stability. The Si clusters show a large programming window even after 90 h storage at the elevated temparature. This implies, that Si clusters seem to be more promising for non-volatile memory applications. However, Ge clusters could be interesting for memory applications which do not require long retention times.