Optimizing Nanocrystal Synthesis For Multi-Dot Floating Gates of Novel Nonvolatile Memories

The synthesis of a single monolayer of nanocrystals (NCs) with a maximum density but no in-plane electrical percolation paths is a challenging task. Such layers are required for the fabrica-tion of multi-dot nonvolatile memories. Here, compared to the conventional nonvolatile memory, the floating gate is replaced by a layer of Si NCs allowing for distributed charge storage and, therefore, lower operation voltages, faster programming, etc. These advantages are lost at too high NC densities when NC’s charge can spread over neighboring NCs by electron tun-neling, i.e. due to electrical in-plane percolation paths.
In this contribution, studies on the synthesis of Si NCs by low energy Si+ implantation into thin gate oxides of NC memories are presented. Using a kinetic 3D lattice Monte Carlo code, the nucleation, growth and Ostwald ripening of the Si NCs in Si supersaturation is simulated. On the basis of these simula-tions, the dependence of the Si NC density, the distribution of the NC spacing as well as the threshold for extended electron tunneling paths are predicted. Thus, process conditions could be identified, where NCs align in a thin layer at high density but sufficient electrical isolation.