Self-aligned doubly-stacked Si dots fabrication for improved data retention of nanocrystal memories

Nonvolatile nanocluster (NC) memories fabricated by Si ion implantation/irradiation of SiO₂ gate oxides have some key parameters which are superior to those of state-of-the-art devices [1-3]. However, data retention is still below industrial requirements. Former studies have proven that a doubly-stacked nanocluster structure can improve retention considerably [4]. However, it is difficult to fabricate NC pairs with a precise intercluster spacing at a precise distance above the Si substrate. Here, based on atomistic process simulations, a novel fabrication technique of self-aligned doubly-stacked Si NCs will be presented. It is assumed that a layer of large (<10nm) Si NCs is placed on top of ~10nm oxide by a conventional (e.g. CVD) technique. This structure is covered by a control oxide. Tiny (~3nm),self-aligned NCs between the large NCs and the substrate form during annealing after energetic ion irradiation. As described in ref.[5], ion beam mixing at Si/SiO₂ interfaces results in Si NCs growth. Here, mixing from the substrate and large NCs lead to selective NC formation below the large NCs. The stability of this CMOS-compatible processing will be evaluated.
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[2] P. Dimikratis et al., J.Phys.Conf.Ser. 10, 7 (2005).
[3] T. Müller, K.-H. Heinig et al., Appl. Phys. Lett. 85, 2373 (2004).
[4] R. Ohba et al., IEEE Trans. El. Dev. 49, 1392 (2002).
[5] K.-H. Heinig et al., Appl. Phys. A 77, 17–25 (2003).