Ion irradiation and ion beam mixing
Ion irradiation not only causes supersaturation and damage to the substrate but also affects the interface between a thin layer and the substrate or interfaces between thin stacked layers. As schematically shown in the figure primary energetic ions produce collisional cascades which cause substantial interface mixing leading to non-stoichiometric and non-stable phases near the interface. Subsequent annealing restores the interface region rapidly via spinodal decomposition. However, the tails of the mixing profiles do not reach the recovered interfaces by diffusion, thus, phase separation proceeds via nucleation and growth of NCs near the interface. The competition between interface restoration and nucleation self-aligns nearly monodispersive δ-layers of NCs in proximity to the interface. For example, self-organization of NC δ-layers in SiO2 has been found close to the Si/SiO2 interface after appropriate Ge+ implantation into a SiO2 layer as well as after Si+ irradiation through SiO2/Si interfaces. The finding that due to ion irradiation Si NCs self-align at a certain distance to the SiO2/Si interface is of great interest for the development and fabrication of new nonvolatile memory integrated circuits.
The self-alignment of d-layers of Si NCs with SiO2/Si interfaces has been predicted by atomistic computer simulations in our Institute. The figure shows the results of Si+ ion irradiation (E = 50 keV, D = 1x1016 cm-2) through a layer stack of 50 nm poly-Si, 15 nm SiO2, into the Si substrate. In the left column KLMC simulation snapshots for (a) the as-irradiated state and (b) after annealing (phase separation) are shown and compared withcorresponding energy-filtered XTEM images of the MOS-like Si/SiO2/Si structure given in the right column. As can be seenthe atomistic simulations and XTEM images are in good agreement (L. Röntzsch et al., phys. stat. Sol. 202, R 170, 2005).
This new approach for ion irradiation induced self-alignment of Si NCs near SiO2/Si interfaces have been applied to the fabrication of non-volatile multi-dot floating-gate memory devices. The fabricated nMOS transistors exhibit significant memory windows at low voltage programming conditions (Vpp=±6 V, tpp= 10 ms). The endurance of 107write/erase cycles is acceptable but data retention is still too low for true EEPROM application.