The nELBE (n,nγ) Trigger Logic

(old version up to April 2010)

The trigger logic of the nELBE detector setup for inelastic neutron scattering is realized by means of a FPGA logic based on the CAEN V1495 General Purpose Board. We developed a firmware for the "User FPGA" of this module that contains all logic functions needed for a proper operation of our setup.

The module processes up to 81 input signals and releases 63 output signals. The meaning of these signals is shown below. All parameters needed by the logical functions can be modified via VME write access to the corresponding register. The register Address Map is also shown below.

The logic schema is shown in the picture below. The input signals are the CFD signals of all PMTs of the plastic and BaF₂ scintillators, which have to be reduced in length and adjusted in time, so that they fulfil the coincidence conditions needed. The coincidence between both PMTs of every single plastic or BaF₂ is done by the FPGA firmware. For every Coincidence an output signal is produced for scaling purpose. Each coincidence signal can be downscaled by an arbitrary factor. From the coincidence signal of all plastic detectors the logical OR is produced, from all BaF₂ detectors a majority signal. Both signals can be downscaled, too. From these signals and two single input signal (Fission chamber and Testpulse) a global OR, the Trigger, is created. The generation of the Trigger is disabled if any Veto signal is present.

The Trigger can be used to start the data acquisition of each DAQ module. Additionally a downscaled Trigger is produced that can be used to force the data readout by, e.g., the RIO power PCs.

 

Inputs:

(all inputs have to be ECL or LVDS)

Port : Channel		Signal	Used for
A	0	Neutron Detector ch00	Plastic 1, Base a
	1	Neutron Detector ch01	Plastic 1, Base b
	2	Neutron Detector ch02	Plastic 2, Base a
	...	...	...
	11	Neutron Detector ch11	Plastic 5, Base b
	12	Neutron Detector ch12
	...	...
	15	Neutron Detector ch15
	16	not used
	...	...
	29	not used
	30	Test pulse 1	Fission Chamber
	31	Test pulse 2	Scaler 3 control output 5
B	0	Veto ch00	Busy BaF2 TAPS module 1
	...	...	...
	7	Veto ch07	Busy BaF2TAPS module 8
	8	Veto ch11	Busy plastic TAPS module 1
	...	...	...
	10	Veto ch10	Busy plastic TAPS module 3
	11	Veto ch11	Busy ADC
	12	Veto ch12	Total Dead Time Plastic Branch
	13	Veto ch13	Total Dead Time BaF2 Branch
	14	Veto ch14	Trigger FPGA output F11
	15	Veto ch15
	...	...
	30	Veto ch30
	31	not used
D	0	BaF2 Detector ch00	BaF2 1, Base a
	1	BaF2 Detector ch01	BaF2 1, Base b
	2	BaF2 Detector ch02	BaF2 2, Base a
	...	...	...
	31	BaF2 Detector ch31	BaF2 16, Base b

Outputs:

Port : Channel		Signal	Used for
E (ECL)	0	Plastic 1 Coincidence	Scaler
	...	...	...
	7	Plastic 8 Coincidence	Scaler
	8	BaF2 1 Coincidence	Scaler
	...	...	...
	23	BaF2 16 Coincidence	Scaler
	24	Plastic OR	Scaler
	25	BaF2 Majority	Scaler
	26	Global OR	Scaler
	27	Trigger	Scaler
	28	Downscaled Trigger	Scaler
	29	not used
	...	...
	31	not used
F (ECL)	0	downscaled Trigger	T1 Trigger
	1	Gate 1	Comm for Plastic TAPS
	2	Gate 2	Comm for BaF2 TAPS
	3	Gate 3	ADC Gate
	4	Trigger	TDC 1 input ch00
	5	Trigger	TDC 1 Trigger
	6	Trigger	TDC 2 input ch00
	7	Trigger	TDC 2 Trigger
	8	Trigger	Testpulse for Plastic TAPS
	9	Trigger	Testpulse for BaF2 TAPS
	10	Trigger	Scaler 1 input ch28
	11	Trigger	FPGA input B14
	12	Veto
	13	Veto	TDC 1 input ch31 (twisted)
	14	Veto	Scaler 1 control input 4
	15	Veto	Scaler 2 control input 4
	16	Plastic 1 Coincidence	Scaler 1 input 2
	17	Plastic 2 Coincidence
	18	Plastic 3 Coincidence	Scaler 1 input 3
	19	Plastic 4 Coincidence
	20	Plastic 5 Coincidence
	21	Plastic 6 Coincidence
	22	"BaF_OR_mdl"
	23	"Glo_OR"
	24	Trigger
	25	"dsca_reset"
	26	Glo_OR_win"
	27	"Pla0001_d"
	28	"Pla0001_l"
	29	"Pla_OR_win"
	30	"sca_LNE"
	31	not Veto
G (NIM)	0	Trigger	Monitoring
	1	Dead Time	Monitoring

Address-Map of User Firmware

(all standard registers with address above BASE + 0x7ffc are still available):

Address BASE +	Register / Content	Data Access		Default Value	Bit range	comment
0x1018	A Mask	D32	R/W	0xFFFFFFFF	31 ... 0	enables channels A:31..00	bit = 0: channel disabled bit = 1: channel enabled
0x101C	B Mask	D32	R/W	0xFFFFFFFF	31 ... 0	enables channels B:31..00
0x1020	C Mask	D32	R/W	0xFFFFFFFF	31 ... 0	enables channels C:31..00
0x1024	D Mask	D32	R/W	0xFFFFFFFF	31 ... 0	enables channels D:31..00
0x1028	E Mask	D32	R/W	0xFFFFFFFF	31 ... 0	enables channels E:31..00
0x102C	F Mask	D32	R/W	0xFFFFFFFF	31 ... 0	enables channels F:31..00
0x1030	ID Mezzanine D	D32	R		2 ... 0	Port D	bit 2..0: type of mezzanine board: b000: A395A b001: A395B b010: A395C b011: A395D
0x1034	ID Mezzanine E	D32	R		2 ... 0	Port E
0x1038	ID Mezzanine F	D32	R		2 ... 0	Port F
0x1048	User FPGA firmware revision	D32	R		15 ... 0	bit 15..8: major revision no. bit 7..0: minor revision no.
0x104C	Scratch register	D32	R/W	0xAFFEAFFE	31 ... 0
0x1050	LED control	D32	R/W	0	8, 1, 0	bit 8: 0 = FPGA controled, 1 = user controled bit 1: 0 = off, 1 = green bit 0: 0 = off, 1 = red
0x1090	GEO address	D32	R/W	0	4 ... 0
0x1100	Control register	D32	R/W	0	5 ... 0	bit 5: FIFO: 1 = clear bit 4: input logic for BaF2s: 0 = AND, 1 = OR bit 3: input logic for plastics: 0 = AND, 1 = OR bit 2: veto length scaler: 0 = enable, 1 = disable bit 1: 1 = reset downscale counter bit 0: 1 = reset veto length scaler
0x1104	BaF2 majority level	D32	R/W	1	15 ... 0	0 = inhibit
0x1108	Majority coincidence window width	D32	R/W	0x00000028	15 ... 0	in units of 25 ns
0x110C	OR coincidence window width	D32	R/W	0x00280028	31 ... 0	bit 31..16: global OR bit 15..0: plastic OR in units of 25 ns
0x1110	Trigger output width	D32	R/W	0x00000064	15 ... 0	in units of 10 ns
0x1114	Gate 1	D32	R/W	0x00320032	31 ... 0	bit 31..16: delay bit 15..0: width in units of 10 ns
0x1118	Gate 2	D32	R/W	0x00320032	31 ... 0
0x111C	Gate 3	D32	R/W	0x00320032	31 ... 0
0x1200	Downscale factors	D32	R/W	0x01010101	31 ... 0	bit 31..24: Plastic 4 bit 23..16: Plastic 3 bit 15..8: Plastic 2 bit 7..0: Plastic 1
0x1204	Downscale factors	D32	R/W	0x01010101	31 ... 0	bit 31..24:  Plastic 8 bit 23..16:  Plastic 7 bit 15..8:  Plastic 6 bit 7..0:  Plastic 5
0x1208	Downscale factors	D32	R/W	0x01010101	31 ... 0	bit 31..24:  BaF2 4 bit 23..16:  BaF2 3 bit 15..8:  BaF2 2 bit 7..0:  BaF2 1
0x120C	Downscale factors	D32	R/W	0x01010101	31 ... 0	bit 31..24:  BaF2 8 bit 23..16:  BaF2 7 bit 15..8:  BaF2 6 bit 7..0:  BaF2 5
0x1210	Downscale factors	D32	R/W	0x01010101	31 ... 0	bit 31..24:  BaF2 12 bit 23..16:  BaF2 11 bit 15..8:  BaF2 10 bit 7..0:  BaF2 9
0x1214	Downscale factors	D32	R/W	0x01010101	31 ... 0	bit 31..24:  BaF2 16 bit 23..16:  BaF2 15 bit 15..8:  BaF2 14 bit 7..0:  BaF2 13
0x1218	Downscale factors	D32	R/W	0x00200101	23 ... 0	bit 23..16:  Trigger bit 15..8:  Majority bit 7..0:  Plastic OR
0x1300	FIFO status	D32	R		17 ... 14, 12 ... 0	bit 17: almost empty (< 4000 words) bit 16: almost full ( > 4000) bit 15: empty bit 14: full bit 12..0: number of words stored
0x1304	FIFO channel enable	D32	R/W	0xFFFFFFFF	31 ...  0	enables veto length measurement bit i: 0 = disable, 1 = enable channel i (channel 31 = total veto)
0x2000	FIFO data	D32	R		31 ...  0