Electronics Scheme of the whole Detector Setup (Up to March 2010)
(old version,latest version)We use the following electronics for the readout of the whole setup:
| RIO (3x) | CES RIO 3 8064 Power PC |
| Trigger Module (2x) | GSI TRIVA3 |
| TDC (2x) | CAEN V1190A 128ch Multihit TDC |
| QDC (2x) | CAEN V792 32ch QDC |
| TAPS Module (11x) | CAEN V874B TAPS 4ch BaF2 Readout |
| Scaler (3x) | SIS 3820 VME Scaler |
| FPGA Trigger Logic (1x) | CAEN V1495 General Purpose Board |
| AND (2x) | CAEN N405 3fold Logic Unit |
| Fan Out (1x) | CAEN N105 Dual Fan-Out 1x16 |
| Gate & Delay Generator (1x) | EG&G GG8000 octal Gate Generator |
| VME Gate & Delay Generator (1x) | CAEN V486 8ch Gate and Delay Generator |
| ECL <-> NIM (1x) | Phillips 726 Level Translator |
| NIM -> ECL (1x) | home made NIM to ECL Converter |
| CFD (2x) | home made 5 fold Constant Fraction Trigger |
Timing Scheme
The timing scheme was produced using a pulse generator (BNC BL-2, settings: rise time = 3 ns, fall time = 30 ns) simulating the detector signals from the two bases of one scintillator panel and one base of a BaF2 detector.
The start time is given relative to the output of the first CFD. Start and length are given in micro seconds.
