Initialization of the VME electronics for (n,fis) experiments
The initialization of the VME modules is controlled via the files "setup.ini". Each line of this file has to have the following structure: "variable = value". Everything behind an double slash "//" is interpreted as a comment. Values can be set decimal or hexadecimal (0x...). Tabs, multiple spaces and empty lines are ignored. A line containing "endnow = 1" will cause MBS to stop reading the setup file, i.e. everything below this line will be ignored.
The following variables are accepted:
setup.ini:
|
Variable |
Meaning |
Value Range |
Recommended |
| General | |||
| comment | defines which comments should be printed out to the mbsprint_vme_0.l log-file | 0: no comments 1: scaler values, errors, initialization 2: data readout information 3: even data send information |
1 |
| testrun | defines if the current setup_vme_0.ini will be copied for logging into the directory "mbsrun/nng/log/" | 0: setup will be saved 1: setup will not be saved |
0 |
| scalerrestart | defines if a check should be enabled at each scaler readout (trigger type 2) if the electronics setup is paralyzed, i.e. if the QDC buffers are full although TDC almost full level not reached | 0: disabled 1: enabled |
1 |
| fastanalysis | defines if a fast analysis of the plastics time-of-flight spectra is written to "mbs_ratios.l" | 0: disabled 1: enabled |
1 |
| printscaler | defines if scaler values are printed out | 0: disabled 1: enabled |
1 |
| bma_readout | defined if data is read in block mode readout BMA (Note: MBS has to be compile with the "#define BMAREADOUT" to use this option) | 0: disabled 1: enabled |
0 |
| print_qdc_error | defines if errors of the QDC are printed out | 0: disabled 1: enabled |
1 |
| print_tdc_error | defines if errors of the TDC are printed out | 0: disabled 1: enabled |
1 |
| Scaler | |||
| sis3820_LNEtime | time between each scaler readout in seconds | 1...420 | 15 |
| ADC | |||
| v556_thrl | ADC lower threshold | 1 | |
| v556_cntr | ADC control register (bit 0..7 = enable channel 1..8) | 0x01 | |
| QDC | |||
| v965a_bset2 | Bit set/clear 2 register (see manual, bits set to 1 are set, bits set to 0 are cleared) | 0x5898 | |
| v985a_iped | Iped value (see manual) | >60 | 80 |
| v965a_ch_ena_high | enable pattern high gain channels | 0xff | |
| v965a_ch_ena_low | enable pattern low gain channels | 0xff | |
| v965a_ch_thr_#_high | high gain threshold of channel #, # = {0...7} | 1 | |
| v965a_ch_thr_#_low | low gain threshold of channel #, # = {0...7} | 1 | |
| TDC | |||
| v1290n_ctrl | control register (see manual) | 0x0228 | |
| v1290n_alm_full | Almost Full level | 1... 32735 | 25000 |
| v1290n_pout | POUT output | 0: Data Ready, 1: Full 2: Almost Full, 3: Error |
2 |
| v1290n_acqmode | acquisition mode | 0x0000: trigger matching 0x0100: continuous storage |
0x0000 |
| v1290n_winwidth | match window width in ns | 25...102375 | 13000 |
| v1290n_winoff | match window offset before trigger in ns | -1000...51200 | 12000 |
| v1290n_extrasearch | extra search margin | 200 | |
| v1290n_reject | reject margin | 100 | |
| v1290n_subtr_mode | enable/disable trigger time subtraction | 0x1400: enable 0x1500: disable |
0x1400 |
| v1290n_edgedet | edge detection mode | 0: pair 1: trailing 2: leading 3: leading + trailing |
2 |
| v1290n_leadres | resolution for leading edge in ps | 25 | |
| v1290n_widthres | resolution for width in ps | 100 | |
| v1290n_headtrail | define if TDC header and trailer are enabled | 0x3000: enabled 0x3100 disabled |
0x3100 |
| v1290n_enable | input channel enable pattern | 0x3fff | |
| Fast analysis | |||
| backmin | ToF cuts: background lower limit | see histogram | |
| backmax | ToF cuts: background upper limit | see histogram | |
| gammamin | ToF cuts: gamma pre peak lower limit | see histogram | |
| gammamax | ToF cuts: gamma pre preak upper limit | see histogram | |
| neutronmin | ToF cuts: neutrons lower limit | see histogram | |
| neutronmax | ToF cuts: neutrons upper limit | see histogram | |
| FPGA | |||
| v1495_reload | defines if the V1495 user FPGA firmware is reloaded before initialization | 0: disabled 1: enabled |
0 |
| v1495_a_mask_l | Port A masking, low bits A[0] ... A[15] (see here) | 0x00ff | |
| v1495_a_mask_h | Port A masking, high bits A[16] ... A[31] | 0x0101 | |
| v1495_b_mask_l | Port B masking, low bits B[0] ... B[15] | 0x0000 | |
| v1495_b_mask_h | Port B masking, high bits B[16] ... B[31] | 0x0000 | |
| v1495_d_mask_l | Port D masking, low bits D[0] ... D[15] (see here) | 0x0003 | |
| v1495_d_mask_h | Port D masking, high bits D[16] ... D[31] | 0x0000 | |
| v1495_e_mask_l | Port E masking, low bits E[0] ... E[15] (see here) | 0x00f3 | |
| v1495_e_mask_h | Port E masking, high bits E[16] ... E[31] | 0x0000 | |
| v1495_f_mask_l | Port F masking, low bits F[0] ... F[15] (see here) | 0xffff | |
| v1495_f_mask_h | Port F masking, high bits F[16] ... F[31] (see here) | 0xffff | |
| v1495_trig_wdth | trigger width in ns (10 ns steps) | 10...655350 | 3000 |
| v1495_trig_delay | TDC trigger delay in ns (10 ns steps) (Has to be smaller than v1495_trig_wdth!) | 10...655350 | 2500 |
| v1495_adc_delay | ADC gate output delay in ns (10 ns steps) | 10...655350 | 60 |
| v1495_adc_gate | ADC gate output width in ns (10 ns steps) | 10...655350 | 100 |
| v1495_qdc_delay | QDC gate output delay in ns (10 ns steps) | 10...655350 | 60 |
| v1495_qdc_gate | QDC gate output width in ns (10 ns steps) | 10...655350 | 100 |
| v1495_trig_scal | downscale factor for readout Trigger | 1...65535 | 31 |
