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Atomic layer etching of SiGe nanowires

Khan, M. B.; Shakeel, S.; Richter, K.; Ghosh, S.; Deb, D.; Hübner, R.; Mikolajick, T.; Erbe, A.; Georgiev, Y.


Developments in the fabrication techniques like lithography, etching, thin-film deposition, and metallization, etc. have enhanced device the performance of the complementary metal-oxide-semiconductor (CMOS) transistors mainly by the scaling-down. Innovative concepts need to be incorporated to further improve the device performance as the scaling limits are being reached.
We report on the development of the atomic layer etching (ALE) process to fabricate smooth SiGe-on-insulator (SiGeOI) nanowire using the conventional dry etching tool. First, nano-patterns were made on SiGeOI samples using electron beam lithography. Then these patterns were transferred into the SiGeOI layer using an inductively coupled plasma reactive ion etching (ICP-RIE) process. Subsequently, the ALE process was developed to smoothen the nanowire and to reduce their widths. For the surface modification step, SF6 was used, while Ar+ was used for the subsequent modified layer removal step. The ALE cycle sequence was: modification with 60 sccm SF6 for 20 s, 60 sccm Ar purge for 15 s, layer removal with 60 sccm Ar for 10 s using 25 W platen power, and 40 sccm Ar purge for 10 s.
Various ALE cycles were performed to investigate the effect of ALE on the nanowire roughness and width. The surface of etched features was studied using the atomic force microscopy (AFM) (figure 1 (a)). A reduction in the width of the wire was seen with the increasing number of the ALE cycles. Figure 1 (b) shows the root mean square (r.m.s) surface roughness of the buried oxide after certain numbers of the ALE cycles. The roughness went down from ca. 6 nm to 1 nm or below (exact value could not be calculated due to limitation of the AFM tip) as the number of ALE cycles was increased from 78 to 102.
Figure 2 shows sub-12 nm nanowires with smooth sidewalls fabricated after performing 63 ALE cycles. An etch per cycle of 1.1 Å was attained. This process, developed on a conventional ICP-RIE tool, can be used to further scale down the nanowires.

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